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White Electronic Designs
2Mx8 MONOLITHIC FLASH, SMD 5962-97609
FEATURES
Access Times of 90, 120, 150ns Packaging: * 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207). Fits standard 56 SSOP footprint. * 44 pin Ceramic LCC** Sector Architecture * 32 equal size sectors of 64KBytes each * Any combination of sectors can be erased. Also supports full chip erase. 100,000 Write/Erase Cycles Minimum Organized as 2Mx8 Commercial, Industrial, and Military Temperature Ranges 5V Read and Write. 5V 10% Supply. Low Power CMOS
WMF2M8-XXX5
Data# Polling and Toggle Bit feature for detection of program or erase cycle completion. Supports reading or programming data to a sector not being erased. RESET# pin resets internal state machine to the read mode. Multiple Ground Pins for Low Noise Operation
* This data sheet describes a product that is subject to change without notice. ** Package to be developed. Note: For programming information refer to Flash Programming 16M5 Application Note.
Fig. 1 - Pin Configuration for WMF2M8-XXX5 56 CSOP Top View
CS# A12 A13 A14 A15 NC NC NC A20 A19 A18 A17 A16 VCC GND I/O6 NC I/O7 NC RY/BY# OE# WE# NC NC I/O5 NC I/O4 VCC
Pin Description
NC RESET# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC NC I/O1 NC I/O0 A0 NC NC NC I/O2 NC I/O3 NC GND
44 CLCC** Top View
RESET# CS# VCC A10 A12 A13 A14 A15 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 GND GND I/O7 A16 A17 A18 A19 NC NC NC A20 WE# OE# RY/BY# A11 A8 A7 A6 A5 A4 NC NC NC A3 A2 A1 A0 7 8 9 10 11 12 13 14 15 16 17 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
I/O0-7 A0-20 WE# CS# OE# VCC GND RY/BY# RESET#
Data Inputs/Outputs Address Inputs Write Enable Chip Select Output Enable Power Supply Ground Ready/Busy Reset
6 5 4 3 2 1 44 43 42 41 40
** Package to be developed.
May 2004 Rev. 6
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ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Ratings Unit Voltage on Any Pin Relative to VSS VT -2.0 to +7.0 V Power Dissipation PT 8 W Storage Temperature TSTG -65 to +125 C Short Circuit Output Current IOS 100 mA Endurance - Write/Erase Cycles (Mil Temp) 100,000 min cycles Data Retention (Mil Temp) 20 years
WMF2M8-XXX5
CAPACITANCE
TA = +25C
Parameter Address Input capacitance Output Enable capacitance Write Enable capacitance Chip Select capacitance Data I/O capacitance Symbol CAD COE CWE CCS CI/O Conditions Max Unit VI/O = 0 V, f = 1.0MHz 12 pF VIN = 0 V, f = 1.0MHz 12 pF VIN = 0 V, f = 1.0MHz 12 pF VIN = 0 V, f = 1.0MHz 12 pF VI/O = 0 V, f = 1.0MHz 12 pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Supply Voltage VCC 4.5 Ground VSS 0 Input High Voltage VIH 2.0 Input Low Voltage VIL -0.5 Operating Temperature (Mil.) TA -55 Operating Temperature (Ind.) TA -40 Typ 5.0 0 Max 5.5 0 VCC + 0.5 +0.8 +125 +85 Unit V V V V C C
DC CHARACTERISTICS -- CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55C TA +125C
Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2) VCC Standby Current Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH VLKO Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz CS# = VIL, OE# = VIH VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = Vcc 0.3V IOL = 12.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 Min Max 10 10 40 60 2.0 0.45 4.2 Unit A A mA mA mA V V V
0.85xVCC 3.2
NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH. 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
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VCC = 5.0V, VSS = 0V, -55C TA +125C
Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (1) Sector Erase (2) Read Recovery Time before Write VCC Setup Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4) RESET# Pulse Width
NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling.
WMF2M8-XXX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
Symbol tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tWPH Min 90 0 45 0 45 0 45 20 -90 Max Min 120 0 50 0 50 0 50 20 -120 Max Min 150 0 50 0 50 0 50 20 -150 Max ns ns ns ns ns ns ns ns s sec s s sec sec ns ns Unit
300 15 0 50 44 256 tOEH tRP 10 500 10 500 0 50
300 15 0 50 44 256 10 500
300 15
44 256
AC CHARACTERISTICS - READ-ONLY OPERATIONS
VCC = 5.0V, VSS = 0V, -55C TA +125C
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Enable Hold Time Symbol tAVAV tAVQV tELQV tGLQV Read Toggle & Data Polling tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tOEH 10 tDF tDF tOH tReady 20 20 0 20 0 20 10 30 30 0 20 10 35 35 ns ns ns ns s Min 90 -90 Max 90 90 40 0 0 Min 120 -120 Max 120 120 50 0 Min 150 -150 Max 150 150 55 ns ns ns ns ns Unit
Chip Select High to Output High Z (1) Output Enable High to Output High Z (1) Output Hold from Addresses, CS# or OE# Change, whichever is First RESET# Low to Read Mode (1)
1. Guaranteed by design, not tested.
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VCC = 5.0V, VSS = 0V, VSS = 0V, -55C TA +125C
Parameter Write Cycle Time Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High Duration of Byte Programming Operation (1) Sector Erase Time (2) Read Recovery Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4)
NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec.
WMF2M8-XXX5
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
Symbol tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL tWC tWS tCP tAS tDS tDH tAH tCPH Min 90 0 45 0 45 0 45 20 -90 Max Min 120 0 50 0 50 0 50 20 -120 Max Min 150 0 50 0 50 0 50 20 -150 Max ns ns ns ns ns ns ns ns s sec s sec sec ns Unit
300 15 0 44 256 tOEH 10 10 0
300 15 0 44 256 10
300 15 44 256
3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling.
FIGURE 2 - AC TEST CIRCUIT AC Test Conditions
IOL Current Source
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level
VZ = 1.5V (Bipolar Supply)
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
D.U.T. Ceff = 50 pf
Output Timing Reference Level
IOL Current Source
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
HARDWARE RESET (RESET#)
Parameter Std tREADY tREADY tRP tRH tRB Description RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) RESET Pulse Width RESET High Time Before Read (See Note) RY/BY Recovery Time Test Setup Max Max Min Min Min All Speed Options 20 500 500 50 0 Unit s ns ns ns ns
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FIGURE 3 - RESET# TIMING
WMF2M8-XXX5
RY/BY#
CS#, OE# tRH RESET#
tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CS#, OE#
RESET#
tRP
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WMF2M8-XXX5
FIGURE 4 - AC WAVEFORMS FOR READ OPERATIONS
tRC Addresses tACC CS# tDF Addresses Stable
OE# tOEH WE# HIGH Z Outputs tCE
tOE
tOH HIGH Z Output Valid
RESET# RY/BY#
0V
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WMF2M8-XXX5
FIGURE 5 - WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CS# OE# tWP WE# tCS tDS tDH Data
A0h PD
Read Status Data (last two cycles)
PA
PA
tCH
tWHWH1
tWPH
Status tBUSY
DOUT
tRB
RY/BY# tVCS
VCC
Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of a four bus cycle sequence.
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WMF2M8-XXX5
FIGURE 6 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
tWC Addresses 2AAh
tAS SA 555h for chip erase tAH
VA
VA
CS#
OE# tWP WE#
tC tCS
tCH
tWPH tDS tDH
tWHWH2
Data
55h
30h 10 for CHip Erase tBUSY
In Progress
Complete
tRB
RY/BY# tVCS
VCC
Notes: SA is the sector address for Sector Erase.
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WMF2M8-XXX5
FIG. 7 - AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALIGORITHM OPERATIONS
tRC
Addresses
VA tACC
VA
VA
CS#
tCH
tCE
tOE tOEH tDF tOH
OE# WE# DQ7 DQ0-DQ6
tBUSY Complement Complement True Valid Data High Z
High Z Status Data Status Data True Valid Data
RY/BY#
Notes: VA = Valid Address. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
May 2004 Rev. 6
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WMF2M8-XXX5
FIGURE 8 - ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
XXX for program PA for program SA for sector erase XXX for erase XXX for chip erase
Data Polling PA
Addresses
tWC tWH tAS tAH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CS#
tWS
tCPH tDS tDH tBUSY
Data
tRH AO for program 55 for erase PD for program 30 for sector erase 10 for chip erase
DQ7
DOUT
RESET#
RY/BY#
Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of a four bus cycle sequence.
May 2004 Rev. 6
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WMF2M8-XXX5
FIGURE 9 - TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
Addresses
VA tACC
VA
VA
VA
CS#
tCH
tCE
OE#
tOEH
tOE tDF tOH
WE# DQ6-DQ2
tBUSY High Z Valid Status (first read) Valid Status (second read) Valid Status (stops toggling)
Valid Data
RY/BY#
Notes: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle and array data read cycle.
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FIGURE 10 - DQ2 VS. DQ6
WMF2M8-XXX5
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Enter Embedded Erasing Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: The system may use OE# or CS# to toggle DQ2 and DQ6. DQ6 toggles only when read at an address within the erase-suspended sector.
TEMPORARY SECTOR UNPROTECTED
Parameter Std tVIDR tRSP
Note: Not 100% tested.
Description VID Rise and Fall time (see notes) RESET# setup time for temporary sector unprotect Min Min
All Speed Options 500 4
Unit ns ms
FIGURE 11 - TEMPORARY SECTOR GROUP UNPROTECTED TIMINGS
12V RESET#
0 or 5V
tVIDR Program or Erase Command Sequence tVIDR
0 or 5V
CS#
WE#
tRSP
RY/BY#
May 2004 Rev. 6
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PACKAGE 207: 56 LEAD, CERAMIC SOP
23.63 (0.930) 0.25 (0.010) 21.59 (0.850) TYP 0.18 (0.007) 0.05 (0.002)
WMF2M8-XXX5
2.87 (0.113) MAX 1.02 (0.040) 0.18 (0.007) 16.13 (0.635) 0.13 (0.005) 12.96 (0.510) 0.15 (0.006) 1.60 (0.063) TYP + + PIN 1 IDENTIFIER 0.25 (0.010) 0.05 (0.002) SEE DETAIL "A" 4.06 (0.160) MAX 0.51 (0.020) TYP
0.80 (0.031) TYP
R = 0.18 (0.007) TYP 0 / -4 DETAIL "A"
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE DIMENSION: 44 LEAD, CERAMIC LCC**
12.70 (0.500) TYP 1.27 (0.050) TYP
0.53 (0.021) 0.74 (0.029)
12.70 (0.500) TYP
PIN 1
1.14 (0.045) 1.40 (0.055)
16.26 (0.640) 16.67 (0.660)
3.05 (0.120) MAX
16.26 (0.640) 16.67 (0.660)
PIN 1 IDENTIFIER
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ** Package to be developed.
May 2004 Rev. 6 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ORDERING INFORMATION
WMF2M8-XXX5
W M F 2M 8 - XXX X X 5 X
LEAD FINISH: Blank = A = Gold plated leads Solder dip leads
VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: M = Military, 883 Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to +70C
PACKAGE TYPE: DA = 56 Lead CSOP (Package 207) fits standard 56 SSOP footprint L = 44 Lead Ceramic LCC* ACCESS TIME (ns) ORGANIZATION, 2M x 8 Flash MONOLITHIC WHITE ELECTRONIC DESIGNS CORP.
* Package to be developed.
Device Type 2M x 8 Flash Monolithic 2M x 8 Flash Monolithic 2M x 8 Flash Monolithic
Sector Size 64KByte 64KByte 64KByte
Speed 150ns 120ns 90ns
Package 56 lead CSOP (DA) 56 lead CSOP (DA) 56 lead CSOP (DA)
SMD No. 5962-97609 01HXX 5962-97609 02HXX 5962-97609 03HXX
May 2004 Rev. 6
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